Field of Invention
The present invention relates to a transistor and a method of manufacturing the same.
Description of Related Art
Metal oxide semiconductor transistors are thin-film transistors that utilize metal oxides as semiconductor layers. As compared with the amorphous silicon thin-film transistors, metal oxide semiconductor transistors have a higher carrier mobility and thus have a better electrical performance. In addition, since the manufacturing method of the metal oxide semiconductor transistors is simpler than the manufacturing method of low temperature polysilicon thin-film transistors, the productive efficiency of metal oxide semiconductor transistors is higher. In recent years, the industry has developed “self-aligned” processes for metal oxide semiconductor transistors to further reduce the length of the channel region so as to improve the electrical performance of the metal oxide semiconductor transistors.
FIG. 1 to FIG. 4 schematically depict cross-sectional diagrams illustrating a method of manufacturing a self-aligned transistor at various stages, according to the prior art. In FIG. 1, a metal-oxide semiconductor layer 20 is first formed over a substrate 21. Then, a source electrode 30 and a drain electrode 32 are formed on opposite sides of the metal-oxide semiconductor layer 20. After that, a dielectric layer 40 is formed to cover the metal-oxide semiconductor layer 20, the source electrode 30, and the drain electrode 32. After the dielectric layer 40 is formed, a gate electrode 50 is formed over the dielectric layer 40.
Subsequently, with reference to FIG. 2, the gate electrode 50 is used as a mask to perform an etching process so as to remove the portion of the dielectric layer 40 that is not covered by the gate electrode 50. A gate dielectric layer 52 is therefore formed underneath the gate electrode 50. The etching process allows the source electrode 30, the drain electrode 32, and portions of the metal-oxide semiconductor layer 20 to be exposed.
Thereafter, with reference to FIG. 3, a doping process is carried out onto the exposed portions of the metal-oxide semiconductor layer 20, using the gate electrode 50, the source electrode 30, and the drain electrode 32 as masks, so as to form a source region 20S and a drain region 20D in the metal-oxide semiconductor layer 20. The undoped portion of the metal-oxide semiconductor layer 20 under the gate electrode 50 form a channel region 20C. The length B of the channel region 20C is substantially determined by the width of the gate electrode 50.
However, the conventional method tends to have the problem that the process margin of the etching process is too narrow. FIG. 4 schematically depicts a cross-sectional view of some implementations after the etching process. As shown in FIG. 4, an over-etch phenomenon occurs in some area of the substrate, and that causes problems such as possible collapse of the gate electrode 50 and the difficulty in controlling the length of the channel region 20C. With the development of large-size manufacturing technology in display and semiconductor techniques, the problem of narrow process margin in the etching process becomes increasingly serious. In view of the above, there is a need for an improved metal oxide semiconductor transistor and a manufacturing method thereof.